High data reliability, high speed of memory access, reduced chip size and reduced power consumption are features that are demanded from semiconductor memory.
In conventional peripheral circuitries for a semiconductor device, for example, pads and data queue circuits (or data input/output circuits) are arranged in a corresponding manner across layers. The data queue circuit or data input/output circuit is called collectively “DQ circuit” hereinafter. FIG. 1 is a schematic diagram of peripheral circuitries around external terminals in a semiconductor device. Each pad, which is configured to be coupled to an external circuitry outside the semiconductor device, is located in proximity to (e.g., immediately above) its respective DQ circuit in order to keep wirings between the pads and the DQ circuits the same length that is sufficiently short to have the same low impedance. In recent years, there has been an effort to reduce an area of a peripheral circuit region that is occupied by peripheral circuitries included on a semiconductor die of a memory device. For example, a size of each DQ circuit has become even smaller in order to improve driving ability for faster operations by shorter wirings (e.g., a clock signal line CLK, which provides a clock signal to the DQ circuits).